Liquid crystal display and method for driving thereof

ABSTRACT

The present invention relates to a liquid crystal display and a driving method thereof. A liquid crystal display according to the present invention comprises: a liquid crystal panel assembly including a plurality of gate lines, a plurality of data lines which are insulated from and intersects the gate lines, and a plurality of pixels each of which is formed in an area defined by the data line and the gate line and has a switching element connected to the gate line and the data line; a gate driver for supplying gate voltages to the gate lines; at least one data driver for supplying data voltages corresponding to image data to the data lines; and a timing controller for comparing nth image data applied from outside and (n−1)th image data stored therein and selectively providing the nth image data to the data driver depending on the comparison result. According to the present invention, since image data transmission between the timing controller and the data driver can be minimized, power consumption and EMI due to image data switching can be reduced.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a liquid crystal display and a drivingmethod thereof.

(b) Description of Related Art

Recently, it is required for display devices to become lighter andthinner, as personal computers and televisions become lighter andthinner. To meet these requirements, flat panel displays such as aliquid crystal display (LCD) has been developing instead of a cathoderay tube (CRT).

An LCD is a display device that obtains intended image signal byapplying electric field to liquid crystal material having dielectricanisotropy, which is interposed between two panels, and controlling theintensity of the electric field to adjust the transmittance of lightpassing through the panels. The LCD is a representative one amongportable flat panel displays (FPDs), and the most popular one amongthose LCDs is a TFT-LCD using thin film transistors (TFTs) as switchingelements.

A conventional LCD includes a plurality of gate lines transmitting scansignals, a plurality of data lines intersecting the gate lines andtransmitting image data, and a plurality of pixels formed in areasdefined by the gate lines and the data lines in a matrix and connectedto the gate lines and the data lines via respective switching elements.

To apply image data to each pixel of an LCD, gate on signals, which arescanning signals, are sequentially applied to the gate lines to turn onthe switching elements connected thereto, and image data (morespecifically, gray voltages) to be applied to a pixel line correspondingto the gate line are provided for each data line simultaneously. Then,image data provided to the data line are applied to the pixels via theswitching elements turned on. If image data are applied to all pixelrows by sequentially applying gate on signals to all gate lines duringone (1) frame period, an image of a frame can be displayed.

A timing controller that controls overall operation of an LCD transmitsthe image data to a data driver IC, and the data driver IC applies thereceived image data to the pixels as described above.

On the other hand, frequency of image data gets larger as the resolutionof an LCD becomes higher. Since a PCB (printed circuit board) cannotdeal with the increased frequency, the number of buses that transmitimage data from the timing controller to the data driver IC should beincreased. Then, EMI (electro magnetic interference) of an LCD increasesas well as power consumption. Therefore, the transmission method ofimage data from the timing controller to the driver IC becomes moreimportant.

Since the timing controller of an LCD transforms the image data to 8-bitbinary codes and transmits them to the driving IC via data bus, codetransition between the current data and the next data is frequentlygenerated, which increases power consumption.

That is, since power consumption during data transmission can beexpressed as P=cV²f (where c is a capacitance of a PCB, V is a swingwidth of voltage, and f is a frequency of image data transition), powerconsumption increases as data transition occurs more frequently duringdata transmission.

SUMMARY OF THE INVENTION

Therefore, the present invention is directed to reduce power consumptionduring image data transmission of an LCD.

According to a first aspect of the present invention, an LCD including aliquid crystal panel assembly, a gate driver, at least one data driver,and a timing controller is provided. The liquid crystal panel assemblyincludes a plurality of gate lines, a plurality of data lines which areinsulated from and intersects the gate lines, and a plurality of pixelseach of which is formed in an area defined by the data line and the gateline and has a switching element connected to the gate line and the dataline. The gate driver supplies gate voltages to the gate lines, and thedata drivers supply data voltages corresponding to image data to thedata lines. The timing controller compares nth image data applied fromoutside and (n−1)th image data stored therein and selectively providesthe nth image data to the data driver depending on the comparison result

The timing controller generates an operation control signal based on thecomparison result and provides the operation control signal to the datadriver, and the data driver is operated with a mode, based on theoperation control signal, selected from a holding mode which providesdata voltages corresponding to the stored (n−1)th image data, aninverting mode which provides data voltages corresponding to theinverted (n−1)th image data, and an updating mode which provides datavoltages corresponding to the nth image data provided from the timingcontroller.

The timing controller includes a first line memory for storing the nthimage data applied from outside; a second line memory in which the(n−1)th image data applied in advance are stored; and a control signalgenerator for generating an operation control signal after comparing thenth image data and the (n−1)th image data.

The control signal generator generates: an operation control signal of afirst status to let the data driver operate with the holding mode whenall bits of the nth image data and the (n−1)th image data are equal toeach other; an operation control signal of a second status to let thedata driver operate with the inverting mode when all bits of the nthimage data and the (n−1)th image data are complementary to each other;and an operation control signal of a third status to let the data driveroperate with the updating mode when at least one bit of the nth imagedata and at least one corresponding bit of the (n−1)th image data arenot equal or complementary to each other.

It is preferable that the timing controller does not provide the nthimage data to the data driver when all bits of the nth image data andthe (n−1)th image data are equal or complementary to each other.

The timing controller generates an operation control signal whose statuschanges by 1H period by comparing the nth image data and the (n−1)thimage data during 1H period; and the data driver holds, inverts, orupdates the image data by 1H period.

Alternatively, the timing controller generates an operation controlsignal whose status changes as many times as the number of the datadrivers by 1H period by comparing the nth image data and the (n−1)thimage data for each data driver during 1H period; and the data driverholds, inverts, or updates the image data for each data driver.

Alternatively, the timing controller generates an operation controlsignal whose status changes as many times as the number of pixels of aline by 1H period by comparing the nth image data and the (n−1)th imagedata for each pixel during 1H period; and the data driver holds,inverts, or updates the image data for each pixel.

The operation control signal may be a 2-bit signal; and the data driverincludes: an exclusive logical sum operator for performing an exclusivelogical sum operation based on a first bit of the operation controlsignal; a first multiplexer for selecting one, based on the second bitof the operation control signal, from a first input which is a signalprovided from the exclusive logical sum operator and a second inputwhich is image data provided from the timing controller, and outputtingthe selected signal; a D flip-flop for outputting image data providedselectively from the first multiplexer according to a signal applied toa clock terminal; and a logical multiplication operator for a logicalmultiplication operation of the applied data clock signal and a Carrysignal and providing the result to the clock terminal of the Dflip-flop. The data clock signal can be applied when at least one bit ofthe nth image data and at least one corresponding bit of the (n−1)thimage data are not equal or complementary to each other.

According to another aspect of the present invention, a driving methodof an LCD including the steps of: a) providing data voltages accordingto image data to the data line; and b) making the data voltage beapplied to the pixel by providing a gate voltage to the gate line isprovided. The LCD includes a plurality of gate lines, a plurality ofdata lines which are insulated from and intersects the gate lines, and aplurality of pixels each of which is formed in an area defined by thedata line and the gate line and has a switching element connected to thegate line and the data line.

The a) step includes the steps of: comparing (n−1)th image data providedin advance and nth image data being provided currently; providing datavoltages corresponding to the (n−1)th image data to the data line whenall bits of the nth image data and the (n−1)th image data are equal toeach other; inverting the (n−1)th image data and providing data voltagescorresponding thereto when all bits of the nth image data and the(n−1)th image data are complementary to each other; and providing datavoltages corresponding to the nth image data to the data line when atleast one bit of the nth image data and at least one corresponding bitof the (n−1)th image data are not equal or complementary to each other.

The a) step compares the nth image data and the (n−1)th image dataduring 1H period. Alternatively, the a) step compares the nth image dataand the (n−1)th image data for each data driver of the liquid crystaldisplay during 1H period. The a) step may compare the nth image data andthe (n−1)th image data for each pixel during 1H period.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the present invention will become moreapparent by describing preferred embodiments thereof in detail withreference to the accompanying drawings in which:

FIG. 1 is a schematic layout diagram of an LCD according to anembodiment of the present invention;

FIG. 2 is a schematic diagram of a timing controller according to anembodiment of the present invention;

FIG. 3 is a schematic diagram of an LCD according to another embodimentof the present invention;

FIG. 4 is a schematic diagram of a data driver according to a firstexample of the present invention; and

FIG. 5 is a schematic diagram of a data driver according to a secondexample of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the inventions invention are shown. The present invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein.

In the drawings, the thickness of layers and regions are exaggerated forclarity. Like numerals refer to like elements throughout. It will beunderstood that when an element such as a layer, region or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” another element,there are no intervening elements present FIG. 1 is a schematic layoutdiagram of an LCD according to an embodiment of the present invention.

Referring to FIG. 1, an LCD according to an embodiment of the presentinvention includes a liquid crystal panel assembly 1, a gate driver 2, adata driver 3, a driving voltage generator 4, a timing controller 5, anda gray voltage generator 6.

The liquid crystal panel assembly 1 includes two panels (for example, aTFT array panel and a color filter panel). A plurality of gate lines anda plurality of data lines, which intersect each other, are formed on oneof the two panels, and a plurality of pixels are provided in areasdefined by the gate lines and the data lines, each of which includes aTFT which is a switching element whose gate electrode, source electrode,and drain electrode are connected to the gate line, the data line, and apixel electrode, respectively.

The timing controller 5 receives R (red), G (green), and B (blue) datasignals, a vertical synchronization signal Vsync which is a framedistinction signal, a horizontal synchronization signal Hsync which is arow distinction signal, and a main clock signal CLK from a graphiccontroller (not shown) outside of an LCD module, and outputs digitalsignals for driving the gate driver 2 and the data driver 3.

Timing signals that the tuning controller 5 outputs to the gate driver 2include a vertical start signal Vstart for commanding a start ofapplication of a gate ON voltage to apply the gate On voltage to thegate line, a gate clock signal (hereinafter “CPV” signal) forsequentially applying the gate On voltage to each gate line, and a gateOn enable signal OE for enabling an output of the gate driver 2.

Timing signals that the timing controller 5 outputs to the data driver 3include a horizontal start signal Hstart for commanding an input ofdigital data signals [R(0:N), G(0:N), B(0:N)] received from the graphiccontroller to the data driver 3, a signal for commanding an applicationof the data signals, which are transformed to analog signals in the datadriver 3, to the panel (hereinafter “LOAD” signal), and a horizontalclock signal HCLK for a data shift in the data driver 3.

According to an embodiment of the present invention, an operationcontrol signal CTRL is generated and provided to the data driver 3 tolet the data driver 3 hold, invert, or update the inputted image data.

For example, the operation control signal CTRL may have values as listedon Table 1. TABLE 1 CRTL [1:0] Operational mode CRTL[1] CTRL[0] 0 0 Hold0 1 Invert 1 x Update

The data driver 3 is also called as the source driver, and it performs arole of applying voltages to each pixel of the liquid crystal panelassembly 1 by line. More specifically, the data driver 3 stores digitaldata received from the timing controller 5 in a shift register insidethe data driver 3, selects voltages corresponding to each one of thedata when a LOAD signal is received, and transfers the selected voltagesto the liquid crystal panel assembly 1. According to an embodiment ofthe present invention, the data driver 3 determines which image data areprovided from the timing controller 5 based on'the operation controlsignal CTRL[1:0] received from the tiring controller 5, performs adesignated operation on the image data based on the determinationresult, and transmits the image data to the liquid crystal panelassembly 1.

According to Table 1, in case that the operation control signal is ‘00’(CTRL[1:0]=‘00’), the data driver 3 ignores an image data input from thetiming controller 5, and provides the image data stored in the shiftregister instead to the liquid crystal panel assembly 1 according to aLOAD signal. In case that the operation control signal is ‘01’(CTRL[1:0]=‘01’), the data driver 3 ignores an image data input from thetiming controller 5, inverts the image data stored in the shiftregister, and provides the inverted image data to the liquid crystalpanel assembly 1 instead of the image data as those are. On the otherhand, in case that the operation control signal is ‘1x’(CTRL[1:0]=‘01’), the data driver 3 receives image data from the timingcontroller 5, stores them in the shift register, and provides the imagedata to the liquid crystal panel assembly 1 according to a LOAD signal.

The gate driver 2 is also called as the scan driver, and it performs arole of opening a path for data from the data driver 3 to be transmittedto a pixel. Each pixel of the liquid crystal panel assembly 1 is turnedon/off by a TFT, which serves as a switch, and the on/off operation ofthe TFT is performed by applying a prescribed voltage Von or Voff to thegate. The gate driver 2 receives CPV signal and OE signal outputted fromthe timing controller 5 and applies gate ON voltages G1, G2, . . . , Gnsequentially to the gate lines synchronized with the two signals CPV andOE.

The gray voltage generator 6 generates gray voltages divided by thenumber of bit of RGB data provided from the graphic controller (notshown) and provides them to the data driver 3. The data driver 3 isdriven by the signals outputted from the timing controller 5 to applythe data voltages D1, D2, . . . , Dm to all the data lines synchronizedwith driving of the gate driver 2. Assuming that the data voltages D1,D2, . . . , Dm are not influenced very much by delays of the data islines, they are charged to corresponding pixels during the intervalsynchronized with a high interval of the gate ON voltages G1, G2, . . ., Gn.

On the other hand, a Von voltage for turning on the gate of the TFT anda Voff voltage for turning off the gate of the TFT are generated on thedriving voltage generator 4. The driving voltage generator 4 generates aVcom voltage, which is a reference of the data voltage difference in thepixel, as well as the Von and Voff voltages, and Vcom voltage isprovided to a common electrode of each pixel.

According to an embodiment of the present invention, the timingcontroller of an LCD compares image data of a nth line provided from anexternal graphic controller (not shown) (hereinafter “nth image data”)and image data of a (n−1)th line provided in advance (hereinafter“(n−1)th image data”) and outputs an operation control signal to thedata driver without outputting the image data themselves when the twoimage data are equal or complementary to each other to let the datadriver provide data voltages to the liquid crystal panel assembly basedon the (n−1)th image data received in advance. When the two image dataare neither equal nor complementary to each other, the timing controlleroutputs an operation control signal together with the nth image data,and the data driver provides data voltages corresponding to the nthimage data to the liquid crystal panel assembly.

If the timing controller selectively provides image data depending onthe relationship between the nth image data and the (n−1)th image data,power consumption for image data transmission can be reduced.

FIG. 2 is a schematic diagram of a timing controller for comparing imagedata.

Referring to FIG. 2, a timing controller according to an embodiment ofthe present invention includes a first line memory 51 for storing thenth image data Dn applied from outside, a second line memory 52 in whichthe (n−1)th image data Dn−1, which are applied in advance, are stored,and a control signal generator 53 for comparing the nth image data andthe (n−1)th image data and generating an operation control signal.

The control signal generator 53 includes a data comparator 531 forcomparing the nth image data and the (n−1)th image data and outputting afirst signal and a second signal each of which having a value “0” or “1”as a result of comparison, a logical multiplication (AND) operator 532for logical multiplication operation on the first signal outputted fromthe data comparator 531 and a pixel clock signal PC applied thereto tooutput a counting signal, a first counter 533 for counting the countingsignal, a first register 534 for storing the second signal outputtedfrom the data comparator 531, and a signal generator 535 for generatingan operation control signal CTRL based on the signal stored in the firstregister 534 and the count value of the first counter 533.

FIG. 2 shows only a part of the timing controller 5 for generating theoperation control signal while the timing controller 5 according to anembodiment of the present invention includes another parts forprocessing and generating various control signals for driving an LCD,for processing inputted image data, and so forth as well as the elementsdescribed above. However, detailed descriptions of another parts areomitted because those are already known in the art.

Now, an operation of the timing controller 5 according to an embodimentof the present invention for generating an operation control signal isdescribed.

For an 8-bit color XGA (Extended Graphics Array) as an example,horizontal resolution is 1024, and 1 byte is 8 bits. Therefore, eachline memory 51 or 52 includes 3 (R, G, B) pages of 1024 byte memory inwhich 1 byte is 8 bits.

Image data are inputted serially from an external graphic controller(not shown) and stored in the first line memory 51. The data comparator531 compares each 8 bits of the nth image data stored in the first linememory 51 and the (n−1)th image data stored in the second line memory 52and outputs the first signal as “0” if all 8 bits of the two image dataare equal to each other or as “1” if all 8 bits of the two image dataare different from each other. The data comparator 531 outputs thesecond signal as “0” in the above two cases or as “1” if only a part of8 bits of the two image data are equal to or different from each other.

The first signal outputted from the data comparator 531 is inputted tothe AND operator 532 and logically multiplied by the pixel clock signalPC, and the result is inputted to the first counter 533. Therefore, thecounting operation is performed whenever the comparison result of thetwo image data for each pixel is outputted.

After performing the comparison process for 1H period (1 line period),the counting value for the first counter 533 is determined to have “0”,the number of pixels based on the horizontal resolution, for example,“1024”, or a number between “0” and “1024” That is, if the entire imagedata corresponding to the previous line ((n−1)th image data) and thosecorresponding to the present line (nth image data) are equal to eachother, then the counting value is “0”, or if the entire image datacorresponding to the previous line ((n−1)th image data) and thosecorresponding to the present line (nth image data) are complementary toeach other, then the counting value is “1024”. Otherwise, the countingvalue falls between “0” and “1024”.

Therefore, there can be four (4) cases as listed on Table 2 based on thecounting value of the first counter 533 and the value of the firstregister 534. TABLE 2 First First Case counter register Description 1  0 0 All image data of the nth and the (n − 1)th lines are equal 2 10240 All image data of the nth and the (n − 1)th lines are complementary 30 < x < 1024 1 At least 1 byte of the nth and the (n − 1)th lines arenot equal or complementary 4 Don't care 1 At least 1 byte of the nth andthe (n − 1)th lines are not equal or complementary

The timing controller generates the operation control signal having anoperational mode among those listed in Table 1 based on the values ofthe first counter 533 and the first register 534 having respectivevalues among those listed in Table 2. For the cases 1 and 2 of Table 2,the timing controller 5 holds the data output as high impedance statusor as the existing value of “0” or “1” instead of providing the imagedata inputted from outside to the data driver 3 to reduce powerconsumption and EMI generation due to signal transition.

The data driver 3 holds the image data stored in the shift register inadvance ((n−1)th image data) and provides them to the liquid crystalpanel assembly 1, or inverts the (n−1)th image data and provides theinverted image data to the liquid crystal panel assembly 1, or updatesthe image data of the shift register with the image data outputted fromthe timing controller 5 (nth image data) and provides the image data ofthe updated shift register to the liquid crystal panel assembly 1depending on the operation control signal CTRL[1:0] which is generatedbased on the comparison process between image data of the timingcontroller 5.

The above described method of selectively providing image data from thetiming controller 5 to the data driver 3 based on the relationshipbetween the nth image data and the (n−1)th image data can be alsoapplied to an LCD having a plurality of data drivers.

FIG. 3 is a schematic diagram of an LCD having a plurality of datadrivers.

Referring to FIG. 3, a plurality of data drivers 31˜3 m are arranged ina transverse direction. Operation control signals CTRL[1:0] outputtedfrom the timing controller 5 are provided to each data driver 31˜3 m,and various other control signals STH, LOAD, and DCLK are also providedto each data driver 31˜3 m. Although the timing controller 5 and thedata driver 3 are connected using a multi-drop structure that the timingcontroller provides various signals to a plurality of the data driversvia one signal line, the connecting way is not confined to this example,but applicable to a point-to-point structure that the timing controllerprovides various signals to a plurality of the data drivers one-to-onevia respective signal lines.

In an LCD having a plurality of data drivers, each data driver performsan operation of holding, inverting, or updating image data based on theoperation control signal CTRL[1:0].

FIG. 4 is a schematic diagram of a first example of a data driver forprocessing operation control signals. FIG. 4 shows only a part forprocessing the operation control signals while another parts forproviding image data to the liquid crystal panel assembly, for example,a shift register, etc. is not shown because those are already known inthe art.

Referring to FIG. 4, the data driver 3 according to the first example ofthe present invention includes an exclusive logical sum (XOR) operator31 for performing an exclusive logical sum operation based on a firstbit CTRL[0] of the operation control signal, a first multiplexer 32 forselecting one from a first input (a signal provided from the XORoperator) and a second input (image data provided from the timingcontroller) based on a second bit CTRL[1] and outputting the selectedinput, a D flip-flop 34 for outputting image data provided selectivelyfrom the first multiplexer 32 according to a signal applied to a clockterminal, and a logical multiplication (AND) operator 33 for performinga logical multiplication operation on a data clock signal DCLK and aCarry signal and providing the result to the clock terminal of the Dflip-flop 34. An output terminal Q of the D flip-flop 34 is connected toan input terminal of the XOR operator 31.

The Carry signal is an enable signal provided to a shift register of adata driver of a conventional LCD. The data clock signal DCLK is asignal applied as a rule regardless of the relationship between datasuch as those are equal or complementary to each other, for example, italways maintains “H” status.

Referring to FIG. 4, if the timing controller 5 provides an operationcontrol signal CTRL[1:0] having a value “00” based on the fact that allbits of the nth and the (n−1)th image data are equal to each other, theXOR operator 31 outputs “1” based on “0” of the first bit CTRL[0] of theoperation control signal and “0” of the initial output signal of the Dflip-flop 34.

The signal outputted from the XOR operator 31 and the image dataprovided from the timing controller 5 are inputted to a first inputterminal 0 and a second input terminal 1 of the first multiplexer 32,respectively, and the first multiplexer 32 selects the signal inputtedfrom the first input terminal 0 to the D flip-flop 34 because the secondbit CTRL[1] of the operation control signal received via a selectterminal SEL is “0”.

Therefore, if the AND operator 33 outputs “H” signal when a shiftregister of corresponding data driver 3 becomes enabled according thatboth the data clock signal DCLK and the Carry signal are “H” levels, theD flip-flop 34 outputs the output signal “1” of the XOR operator 31provided via an input terminal D.

The signal of “1” outputted from the D flip-flop 34 is inputted to theXOR operator 31 again, and an inverted output terminal /Q of the Dflip-flop 34 outputs a signal of “0”. Therefore, a shift register (notshown) or the like of the data driver 3 holds the stored image data((n−1)th image data) and provides them to the liquid crystal panelassembly 1 based on the signal “0” when a LOAD signal is applied.

On the other hand, if the timing controller 5 provides an operationcontrol signal CTRL[1:0] having a value “01” based on the fact that allbits of the nth and the (n−1)th image data are complementary to eachother, the XOR operator 31 outputs “0”, and the first multiplexer 32selects the output signal of the XOR operator 31 inputted via the firstinput terminal 0, i.e., “0” according to “0” of the second bit CTRL[1]of the operation control signal received via the select terminal SEL andoutputs it to the D flipflop 34. Therefore, a signal of “1” is outputtedvia the inverted output terminal /Q of the D flip-flop 34, and the shiftregister (not shown) or the like inverts the stored image data ((n−1)thimage data) and provides them to the liquid crystal panel assembly 1.

On the other hand, if the operation control signal CTRL[1:0] having avalue of “1x” is provided from the timing controller based on the factthat at least one bit of the nth image data and at least onecorresponding bit of the (n−1)th image data are not equal orcomplementary to each other, the first multiplexer 32 selects the imagedata inputted via the second input terminal 0 (nth image data providedfrom the timing controller) according to “1” of the second bit CTRL[1]of the operation control signal inputted via the select terminal SEL andoutputs it to the D flip-flop 34. Therefore, the nth image data areoutputted via the inverted output terminal /Q of the D flip-flop 34, andthe shift register (not shown) or the like stores the applied nth imagedata and provides them to the liquid crystal panel assembly 1 when aLOAD signal is applied.

According to the first example, the data clock signal DCLK must beprovided continuously, and the LCD can be operated with two operationalmodes as follows.

For a first operational mode, the timing controller compares image datain terms of a data driver and generates an operation control signal foreach data driver when it compares the nth and the (n−1)th image data.Therefore, one operation among holding, inverting, and updating isperformed individually for each data driver. The operation controlsignal CTRL[1:0] experiences the maximum status changes of the number ofthe data drivers during each 1H period.

For a second operational mode, the timing controller compares image datain terms of a pixel and generates an operation control signal for eachpixel when it compares the nth and the (n−1)th image data. Therefore,the data driver performs one operation among holding, inverting, andupdating individually for each pixel. The operation control signalCTRL[1:0] experiences the maximum status changes of the number ofhorizontal resolution during each 1H period.

On the other hand, although the data clock signal DCLK must be appliedconstantly for the data driver driven as the first example, if it isdesired to remove the data clock signal DCLK for the cases 1 and 2, i.e.for the cases that all bits of the nth image data and the (n−1)th imagedata are equal or complementary to each other, an STH signal (starthorizontal signal for correctly latching RGB image data provided from anexternal graphic controller to the data driver) generated from thetiming controller 5 or a signal outputted from the AND operator 33 maybe selectively provided to the clock terminal of the D flip-flop 34based on the second bit CTRL[1] of the operation control signal.

FIG. 5 is a schematic diagram of a second example of a data driveraccording to the present invention. The data driver according to thesecond example has the same structure as the first example shown in FIG.4 except an additional second multiplexer 35 for selectively outputtingone from the signal outputted from the AND operator 33 and the STHsignal based on the second bit CTRL[1] of the operation control signalinputted to the select terminal SEL and providing it to the D flip-flop34.

The data driver acts in the same way as described above except that theD flip-flop 34 outputs a signal of “0” or “1” based on the STH signalwhen all bits of the nth and the (n−1)th image data are equal orcomplementary to each other to make the (n−1)th image data be outputtedas they were or as inverted. The data clock signal DCLK is maintained asDC status.

According to the second example, the timing controller dumps theinformation in the first line memory 51 to the second line memory in aperiod of 1H, an output operation of an operation control signal anddata clock signal as listed in Table 3 is performed based on Table 1 inwhich the values stored in the first counter 533 and the first register534 are listed based on the comparison results of the data comparator531. TABLE 3 Operational Case CTRL[1:0] mode Data and DCLK output 1 00Hold Data: DC (including high impedance) DCLK: DC (including highimpedance) 2 01 Invert Data: DC (including high impedance) DCLK: DC(including high impedance) 3 1x Update Data: output nth image dataTransmit DCLK 4 1x Update Data: output nth image data Transmit DCLK

For his second example, it is preferable that the data comparison isperformed for the entire image data of each line, therefore, theoperation control signal CTRL[1:0] is updated by 1H period.

If the timing controller and the data driver of an LCD have a multi-dropstructure shown in FIG. 3, both the first and the second examples may beapplied.

For a point-to-point structure, the two operational modes of the firstexample can be more easily implemented. This embodiment of the presentinvention is more effective for an LCD for OA. Since the displayenvironment of LCDs used for OA usually corresponds to the case 1 or 2which displays regular images, the timing controller may selectivelyprovide image data to the data driver to reduce the power consumptionwhile it does not affect the image data display.

While the present invention has been described in detail with referenceto the preferred embodiments, it is to be understood that the inventionis not limited to the disclosed embodiments, but, on the contrary, isintended to cover various modifications and equivalent arrangementsincluded within the sprit and scope of the appended claims. For example,the selective image data transmission according to the above-describedembodiments may be performed in a COG (chip on glass) type LCD in whichthe driver is mounted directly on a TFT array panel and the data driveris connected to a printed circuit board via a transmission film. Theimage data transmission according to the above embodiments may beadapted to a structure that the data driver is mounted on a FPC(flexible printed circuit) arranged between a printed circuit board anda TFT array panel.

In addition, the image data transmission methods of the aboveembodiments can be adapted to an LCD which transmits image data usingLVDS (low voltage differential signaling) or RSDS (reduced swingdifferential signaling) method.

Since the application to other examples can be easily performed by theperson skilled in the art, detailed description is omitted.

As shown in the above, since image data transmission between the timingcontroller and the data driver can be minted according to theembodiments of the present invention, power consumption and EMI due toimage data switching can be reduced.

1. A liquid crystal display comprising: a liquid crystal panel assemblyincluding a plurality of gate lines, a plurality of data lines which areinsulated from and intersects the gate lines, and a plurality of pixelseach of which is formed in an area defined by of the data line and thegate line and has a switching element connected to the gate line and thedata line; a gate driver for supplying gate voltages to the gate lines;at least one data driver for supplying data voltages corresponding toimage data to the data lines; and a timing controller for comparing nthimage data applied from outside and (n−1)th image data stored thereinand selectively providing the nth image data to the data driverdepending on the comparison result.
 2. The liquid crystal display ofclaim 1, wherein the timing controller generates an operation controlsignal based on the comparison result and provides the operation controlsignal to the data driver and the data driver is operated with a mode,based on the operation control signal, selected from a holding modewhich provides data voltages corresponding to the stored (n−1)th imagedata, an inverting mode which provides data voltages corresponding tothe inverted (n−1)th image data, and an updating mode which providesdata voltages corresponding to the nth image data provided from thetiming controller.
 3. The liquid crystal display of claim 2, wherein thetiming controller includes: a first line memory for storing the nthimage data applied from outside; a second line memory in which the(n−1)th image data applied in advance are stored; and a control signalgenerator for generating an operation control signal after comparing thenth image data and the (n−1)th image data; and the control signalgenerator generates: an operation control signal of a first status tolet the data driver operate with the holding mode when all bits of thenth image data and the (n−1)th image data are equal to each other; anoperation control signal of a second status to let the data driveroperate with the inverting mode when all bits of the nth image data andthe (n−1)th image data are complementary to each other; and an operationcontrol signal of a third status to let the data driver operate with theupdating mode when at least one bit of the nth image data and at leastone corresponding bit of the (n−1)th image data are not equal orcomplementary to each other.
 4. The liquid crystal display of claim 1,wherein the timing controller does not provide the nth image data to thedata driver when all bits of the nth image data and the (n−1)th imagedata are equal or complementary to each other.
 5. The liquid crystaldisplay of claim 3, wherein the timing controller generates an operationcontrol signal whose status changes by 1H period by comparing the nthimage data and the (n−1)th image data during 1H period and the datadriver holds, inverts, or updates the image data by 1H period.
 6. Theliquid crystal display of claim 3, wherein the timing controllergenerates an operation control signal whose status changes as many timesas the number of the data drivers by 1H period by comparing the nthimage data and the (n−1)th image data for each data driver during 1Hperiod and the data driver holds, inverts, or updates the image data foreach data driver.
 7. The liquid crystal display of claim 3, wherein thetiming controller generates an operation control signal whose statuschanges as many times as the number of pixels of the line by 1H periodby comparing the nth image data and the (n−1)th image data for eachpixel during 1H period and the data driver holds, inverts, or updatesthe image data for each pixel.
 8. The liquid crystal display of claim 2,wherein the operation control signal is a 2-bit signal, and the datadriver includes: an exclusive logical sum operator for performing anexclusive logical sum operation based on a first bit of the operationcontrol signal; a first multiplexer for selecting one, based on a secondbit of the operation control signal, from a first input which is asignal provided from the exclusive logical sum operator and a secondinput which is image data provided from the timing controller andoutputting the selected signal; a D flip-flop for outputting image dataselectively provided from the first multiplexer according to a signalapplied to a clock terminal; and a logical multiplication operator for alogical multiplication operation of the applied data clock signal and aCarry signal and providing a result of the operation to the clockterminal of the D flip-flop.
 9. The liquid crystal display of claim 8,wherein the data clock signal is applied when at least one bit of thenth image data and at least one corresponding bit of the (n−1)th imagedata are not equal or complementary to each other.
 10. The liquidcrystal display of claim 1, wherein the liquid crystal display has a COG(chip on glass) structure.
 11. The liquid crystal display of claim 11,wherein the image data is transmitted to the data driver by RSDS(reduced swing differential signaling).
 12. A driving method of a liquidcrystal display, which includes a plurality of gate lines, a pluralityof data lines which are insulated from and intersects the gate lines,and a plurality of pixels each of which is formed in an area defined bythe data line and the gate line and has a switching element connected tothe gate line and the data line, the method comprising: providing datavoltages according to image data to the data line; and making the datavoltage be applied to the pixel by providing a gate voltage to the gateline, wherein the provision includes: comparing (n−1)th image dataprovided in advance and nth image data being provided currently;providing data voltages corresponding to the (n−1)th image data to thedata line when all bits of the nth image data and the (n−1)th image dataare equal to each other; inverting the (n−1)th image data and providingdata voltages corresponding thereto when all bits of the nth image dataand the (n−1)th image data are complementary to each other; andproviding data voltages corresponding to the nth image data to the dataline when at least one bit of the nth image data and at least onecorresponding bit of the (n−1)th image data are not equal orcomplementary to each other.
 13. The method of claim 12, wherein theprovision compares the nth image data and the (n−1)th image data during1H period.
 14. The method of claim 12, wherein the provision comparesthe nth image data and the (n−1)th image data for each data driver ofthe liquid crystal display during 1H period.
 15. The method of claim 12,wherein the provision compares the nth image data and the (n−1)th imagedata for each pixel during 1H period.